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Miller effect when switching MOSFETs

Release time:

2021-01-12

The basic principle of the Miller plateau formation

The gate drive process of the MOSFET can be simply understood as the charging and discharging process of the input capacitance of the MOSFET (mainly the gate-source capacitance Cgs) by the driving source.

When Cgs reaches the threshold voltage, the MOSFET will enter the on state; after the MOSFET is turned on, Vds begins to decrease, and Id starts to increase, at which point the MOSFET enters the saturation region.

However, due to the Miller effect, Vgs will not rise for a period of time; at this time, Id has reached its maximum, while Vds continues to decrease until the Miller capacitance is fully charged, and Vgs rises to the value of the driving voltage, at which point the MOSFET enters the resistive region, and Vds completely drops, ending the turn-on.

The Miller capacitance prevents the rise of Vgs, thus also preventing the drop of Vds, which prolongs the loss time. (As Vgs rises, the on-resistance decreases, thus Vds drops)

The Miller effect is notorious in MOS driving, and it is caused by the Miller capacitance of the MOS transistor.

During the turn-on process of the MOS transistor, after the GS voltage rises to a certain voltage value, the GS voltage has a stable value for a period of time, after which the GS voltage begins to rise again until fully turned on.

Why is there this stable value?

Because, before the MOS is turned on, the voltage at the D terminal is greater than that at the G terminal, and the charge stored in the parasitic capacitance Cgd of the MOS needs to be injected into the G terminal to neutralize the charge when it turns on, because after the MOS is fully turned on, the voltage at the G terminal is greater than that at the D terminal. The Miller effect will significantly increase the turn-on loss of the MOS. (The MOS cannot quickly enter the switching state)

Thus, the so-called totem pole drive appears! When selecting a MOS, the smaller the Cgd, the smaller the turn-on loss. The Miller effect cannot completely disappear.

The Miller plateau in the MOSFET is actually a typical sign that the MOSFET is in the "amplification region."

Using an oscilloscope to measure the GS voltage, one can see a plateau or dip during the voltage rise process, which is the Miller plateau.

The detailed process of the formation of the Miller plateau

The Miller effect refers to the generation of the Miller plateau during the turn-on process of the MOS transistor, and the principle is as follows.

Theoretically, adding a sufficiently large capacitance between the G and S levels in the driving circuit can eliminate the Miller effect. However, this will prolong the switching time significantly. Generally, it is beneficial to add a capacitance value of 0.1Ciess.

The gentle part of the thick black line in the figure below is the Miller plateau.

In this diagram of the deletion coefficient, at the first turning point: Vds begins to turn on. The change in Vds forms a differential through Cgd and the internal resistance of the driving source. Since Vds decreases approximately linearly, the linear differential is a constant, thus producing a plateau at Vgs.

The Miller plateau is caused by the capacitance at both ends of the MOS's g and d, that is, Crss in the MOS datasheet.

This process is charging Cgd, so the change in Vgs is very small. When Cgd reaches the level of Vgs, Vgs begins to continue rising.

Cgd quickly discharges through the MOS when it just turns on, and then is reverse charged by the driving voltage, sharing the driving current, causing the voltage rise on Cgs to slow down, resulting in a plateau.

t0~t1: Vgs from 0 to Vth. The MOSFET is off, and the current is from the parasitic diode Df.

t1~t2: Vgs from Vth to Va. Id

t2~t3: Vds decreases, causing current to continue through Cgd, the higher Vdd, the longer the time required,

Ig is the driving current.

It starts to drop relatively quickly, and when Vdg approaches zero, Cgd increases. Until Vdg becomes negative, Cgd increases to the maximum, and the drop slows down.

t3~t4: The MOSFET is fully turned on, operating in the resistive region, and Vgs continues to rise to Vgg.

In the later stage of the plateau, VGS continues to increase, and IDS changes very little, which is because the MOS is saturated. However, from the author's diagram, this plateau still has a certain length.

During this plateau period, it can be considered that the MOS is in the amplification phase.

Before the previous turning point: The MOS is in the cutoff period, at this time Cgs is charging, and Vgs approaches Vth.

At the previous turning point: The MOS officially enters the amplification phase.

At the next turning point: The MOS officially exits the amplification phase and begins to enter the saturation phase.

When a voltage V with a slope of dt is applied to the capacitance C (such as the output voltage of the driver), the current inside the capacitance will increase:

I=C×dV/dt (1)

Therefore, when a voltage is applied to the MOSFET, an input current Igate = I1 + I2 will be generated, as shown in the figure below.

Using equation (1) at the voltage node on the right, we can obtain:

I1=Cgd×d(Vgs-Vds)/dt

=Cgd×(dVgs/dt-dVds/dt) (2)

I2=Cgs×d(Vgs/dt) (3)

If a gate-source voltage Vgs is applied to the MOSFET, its drain-source voltage Vds will decrease (even if it decreases non-linearly). Therefore, the negative gain connecting these two voltages can be defined as:

Av=- Vds/Vgs (4)

Substituting equation (4) into equation (2), we can obtain:

I1=Cgd×(1+Av)dVgs/dt (5)

During the transition (turning on or off), the total equivalent capacitance Ceq of the gate-source is:

Igate=I1+I2

=(Cgd×(1+Av)+Cgs)×dVgs/dt

=Ceq×dVgs/dt （6）

The term (1+Av) in the formula is called the Miller effect, which describes the capacitive feedback between the output and input in electronic devices. The Miller effect occurs when the gate-drain voltage approaches zero.

The stage where Cds diverts the most is in the amplification region.

Why? Because the voltage Vd changes most dramatically in this stage. The platform is precisely formed in this stage.

You can think of it this way: the gate current Igate is completely absorbed by Cds, with no current flowing to Cgs.

Pay attention to the representation methods in the data sheet.

Ciss=Cgs+Cgd

Coss=Cds+Cgd

Crss=Cgd

Statement: The content of the above article is organized from the internet. If there are any copyright issues, please contact us immediately.

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