First, let's talk about what electrostatic discharge (ESD) is. It is likely the main culprit causing excessive electrical stress damage to all electronic components or integrated circuit systems.Because static electricity usually has a very high instantaneous voltage (> several thousand volts), this type of damage is catastrophic and permanent, leading to direct burning of the circuit. Therefore, preventing static damage is the number one challenge in all IC design and manufacturing.

 

Static electricity is usually generated by human activities, such as during production, assembly, testing, storage, and transportation, which can cause static to accumulate in the human body, instruments, or equipment. Even the components themselves can accumulate static electricity. When people unknowingly make contact with these charged objects, it creates a discharge path, instantly damaging electronic components or systems due to electrostatic discharge (this is why it was necessary to wear anti-static wrist straps when repairing computers in the past, to prevent human static from damaging chips), similar to how charges stored in clouds can suddenly break through the clouds to create intense lightning, splitting the ground apart, and this usually happens just before rain due to the high humidity in the air that easily forms conductive paths.

So, how can we prevent static discharge damage?First, of course, we should change the environment to reduce static from the source (for example, reducing friction, wearing fewer wool sweaters, controlling air temperature and humidity, etc.), but this is not the focus of our discussion today.

 

Today, we will discuss how to involve protective circuits in the circuit, so that when there is static electricity from the outside, our electronic components or systems can self-protect to avoid being damaged by static electricity (essentially installing a lightning rod).This is also the number one challenge for many IC designers and manufacturers. Many companies have dedicated teams for ESD design. Today, I will start from the most basic theory and gradually explain the principles and points of attention for ESD protection. You will find that the previously discussed PN junction/diodes, transistors, MOSFETs, and snap-back are all used.

 

In previous discussions on the theory of PN junction diodes, we mentioned that diodes have a characteristic:They conduct in the forward direction and are cut off in the reverse direction. Moreover, if the reverse bias voltage continues to increase, avalanche breakdown occurs, leading to conduction. We call this a clamp diode. This is precisely the theoretical basis we need for designing static protection. We utilize this reverse cutoff characteristic to keep this bypass in an open state during normal operation, while when there is external static electricity, this bypass diode undergoes avalanche breakdown, forming a bypass path that protects the internal circuit or gate (isn't it similar to having an overflow outlet in a sink at home to prevent flooding in the bathroom if the faucet is left on?).

 

So the question arises, does this protective circuit become completely dead after breakdown? Is it a one-time use? The answer is certainly no.The breakdown of a PN junction can be divided into two types: electrical breakdown and thermal breakdown. Electrical breakdown refers to avalanche breakdown (low concentration) and Zener breakdown (high concentration). This electrical breakdown is mainly due to carrier collision ionization, producing new electron-hole pairs, so it is recoverable. However, thermal breakdown is not recoverable because heat accumulation causes silicon (Si) to melt and burn out. Therefore, we need to control the current at the moment of conduction, usually by adding a high resistance in series with the protective diode.

 

Additionally, can everyone deduce why the ESD area cannot form silicide?Here’s another theory: ESD usually occurs next to the chip input pad, not inside the chip, because we always want the external static electricity to be discharged as quickly as possible. If placed inside, there will be a delay (note that the chip PAD I dissected earlier has diodes next to it. Some even have two levels of ESD for double protection).

Before discussing the principles and processes of ESD, let's first talk about ESD standards and testing methods. Based on the way static electricity is generated and the different damage modes to circuits, there are usually four types of testing methods.These are: Human Body Model (HBM), Machine Model (MM), Charge Device Model (CDM), and Field-Induced Model (FIM). However, the industry typically uses the first two models for testing (HBM, MM).

 

1. Human Body Model (HBM):This refers to the static charge generated by human friction suddenly contacting the chip, releasing charge and causing the chip to burn out. The reason people often get shocked in the fall is due to this. The industry has traceable ESD standards for HBM (MIL-STD-883C method 3015.7, with an equivalent human capacitance of 100pF and an equivalent human resistance of 1.5Kohm), or the International Electronic Industry Standard (EIA/JESD22-A114-A) also has regulations, depending on which one you want to follow. If it is MIL-STD-883C method 3015.7, it specifies that less than <2kV is Class-1, 2kV~4kV is Class-2, and 4kV~16kV is Class-3.

2. Machine Model (MM):This refers to the static electricity generated by machines (such as robots) moving and discharging through pin contacts when touching the chip. This standard is EIAJ-IC-121 method 20 (or standard EIA/JESD22-A115-A), with an equivalent machine resistance of 0 (because it is metal), and capacitance still at 100pF. Since the machine is metal and has a resistance of 0, the discharge time is very short, almost between ms or us. However, the more important issue is that due to the equivalent resistance being 0, the current is very large, so even a 200V MM discharge is more harmful than a 2kV HBM discharge. Moreover, machines themselves have many wires that can couple with each other, so the current can vary and interfere over time.

The ESD testing method is similar to the GOI testing in FAB. After designating a pin, an ESD voltage is applied for a period of time.Then, we return to test the electrical properties to see if there is any damage. If there are no issues, we apply another step of ESD voltage for a sustained period, then test the electrical properties again, and repeat this until breakdown occurs. The breakdown voltage at this point is the critical voltage for ESD breakdown (ESD failure threshold Voltage). Typically, we apply voltage to the circuit three times (3 zaps) to reduce the testing cycle, usually starting with 70% of the standard ESD threshold voltage, and each step can be adjusted as needed by 50V or 100V.

 

(1). Stress number = 3 Zaps. (5 Zaps, the worst case)
(2). Stress step	ΔVESD = 50V (100V) for VZAP <= 1000V ΔVESD = 100V (250V, 500V) for VZAP > 1000V
(3). Starting VZAP = 70% of averaged ESD failure threshold (VESD)

Additionally, because each chip has many pins, do you test each pin individually or test combinations of pins? Therefore, it can be divided into several combinations:I/O-pin testing (Input and Output pins), pin-to-pin testing, Vdd-Vss testing (from input to output), Analog-pin.

 

1. I/O pins:This means performing ESD testing on both input pins and output pins separately, and since the charge can be positive or negative, there are four combinations: input + positive charge, input + negative charge, output + positive charge, output + negative charge. When testing the input, the output and all other pins are floating; conversely, when testing the output.

2. Pin-to-pin testing: Electrostatic discharge occurs in a loop between pin-to-pin, but if we test every two pins, the combinations become too many. Since any I/O must pass through VDD/Vss to power the entire circuit after applying voltage, the improved version uses a certain I/O pin with positive or negative ESD voltage, while grounding all other I/Os, but the input and output are floating.

3. ESD between Vdd and Vss:You only need to connect Vdd and Vss, and all I/O pins are floating, allowing the static electricity to pass through between Vdd and Vss.

4. Analog-pin discharge testing:Because many analog circuits have differential pairs or operational amplifiers (OP AMP) with two input terminals, to prevent one from damaging and causing differential pairs or operations to fail, ESD testing needs to be done separately, specifically targeting these two pins, while all other pins are floating.

Alright, that's all for the principles and testing of ESD; next, let's talk about the factors in Process and design.

 

With the further miniaturization of Moore's Law, device sizes are getting smaller, junction depths are becoming shallower, and GOX is getting thinner, making electrostatic breakdown easier. Moreover, in advanced processes, the introduction of silicide can make electrostatic breakdown sharper, so almost all chip designs must overcome the problem of electrostatic breakdown.

Electrostatic discharge protection can be addressed from the FAB side of the Process or designed from the IC design side of the Layout.Therefore, you will see that the Process has an ESD option layer, or there are ESD design rules available for customers to choose from in the design rules. Of course, some customers will also design ESD based on the electrical characteristics of the SPICE model through layout.

 

1. ESD in the process:Either change the PN junction or change the load resistance of the PN junction. Changing the PN junction can only rely on ESD_IMP, while changing the load resistance of the PN junction can be done using non-silicide or series resistance methods.

 

1) ESD implant for Source/Drain:Because our LDD structure easily forms two shallow junctions on both sides of the gate poly, and the electric field at the sharp corners of this shallow junction is relatively concentrated, and since it is a shallow junction, it is closer to the Gate, thus being more affected by the terminal electric field of the Gate. Therefore, the ESD discharge capability of such LDD corners is relatively poor (<1kV). If such a device is used at the I/O port, it can easily cause ESD damage. Based on this theory, we need a separate device without LDD, but we need another ESD implant to create a deeper N+_S/D, which can round the sharp corners and move them further from the surface, thus significantly improving ESD breakdown capability (>4kV). However, in this case, the additional MOS Gate must be very long to prevent punchthrough, and since the devices are different, a separate extraction of the device's SPICE model is required.

2) ESD implant for contact holes:A P+ boron implant is placed under the N+ drain of the LDD device, and the depth must exceed that of the N+ drain. This can lower the breakdown voltage of the original Drain (8V-->6V), allowing the Drain to conduct away the breakdown before the LDD corner breaks down, thus protecting the Drain and Gate from breakdown. Therefore, this design can maintain the device size unchanged, and the MOS structure does not change, so there is no need to re-extract the SPICE model. Of course, this method is only applicable to non-silicide processes; otherwise, you cannot implant into the contact.

3) SAB (SAlicide Block):Generally, to reduce the interconnect capacitance of MOS, we use silicide/SAlicide processes. However, if the device operates at the output end, the load resistance of our device decreases, and the external ESD voltage will be easily loaded between the LDD and Gate structures, leading to breakdown damage. Therefore, for the Silicide/Salicide of the output stage MOS, we usually use a SAB (SAlicide Block) mask to block RPO, preventing the formation of silicide. This increases the cost of an additional photo layer, but the ESD voltage can be increased from 1kV to 4kV.

4) Series resistance method:This method does not require adding a mask and is probably the most cost-effective. The principle is somewhat similar to the third method (SAB) of increasing resistance; I deliberately add a series resistance (such as Rs_NW or HiR, etc.), thus achieving the SAB method.

2. ESD in design:This completely relies on the designer's skills. Some companies provide solutions to customers in their design rules, and customers just need to follow the drawings. For those that do not have this, it relies on the customer's own designers. Many design rules state that this is just a guideline/reference, not a guarantee. Generally, the Gate/Source/Bulk are shorted together, and the Drain junction is connected to the I/O end to withstand the ESD surge voltage. NMOS is referred to as GGNMOS (Gate-Grounded NMOS), and PMOS is referred to as GDPMOS (Gate-to-Drain PMOS).

 

Taking NMOS as an example, the principle is that the Gate is in the off state, and the Source/Bulk PN junction is originally shorted to 0 bias. When there is a large voltage at the I/O end, the Drain/Bulk PN junction undergoes avalanche breakdown, causing a large current in the bulk to create a voltage difference with the substrate resistance, leading to forward biasing of the Bulk/Source PN junction. Therefore, the parasitic lateral NPN transistor of this MOS enters the amplification region (emitter junction forward biased, collector junction reverse biased), thus exhibiting Snap-Back characteristics, providing protection. The same reasoning applies to PMOS.

This principle seems simple, but what is the essence (know-how) of the design? How to trigger the BJT? How to maintain Snap-back? How to sustain HBM >2KV or 4KV?

 

How to trigger? There must be sufficient substrate current, so it has developed into the now commonly used multi-finger cross-parallel structure. However, the main technical issue with this structure is that the base width increases, reducing the amplification factor, making Snap-back difficult to turn on. Moreover, as the number of fingers increases, it becomes very difficult to achieve uniform turn-on between each finger, which is also a bottleneck in ESD design.

To change this issue, there are probably two approaches (since the trigger is voltage, improving voltage is either resistance or current): 1. Use SAB (SAlicide-Block) to form a high-resistance non-Silicide area on the I/O Drain, which increases the drain block resistance, making the ESD current distribution more uniform, thereby improving discharge capability; 2. Add a P-ESD (Inner-Pickup imp, similar to the above contact hole P+ ESD imp), by placing a P+ under the N+ Drain, reducing the avalanche breakdown voltage of the Drain, allowing for a larger avalanche breakdown current earlier (see literature paper: Inner Pickup on ESD of multi-finger NMOS.pdf).

 

There are two small pieces of common knowledge about Snap-back ESD that I would like to share with everyone:

1) NMOS usually shows better Snap-back characteristics, but in reality, PMOS is very difficult to have snap-back characteristics,and PMOS generally has better ESD tolerance than NMOS. This is similar to the HCI effect, mainly because NMOS generates electrons during breakdown, which have a high mobility, so Isub is large and easily causes Bulk/Source to conduct forward, but PMOS finds it difficult.

 

2) Trigger voltage/Hold voltage: The trigger voltage is of course the first inflection point (Knee-point) of the snap-back mentioned earlier, the breakdown voltage of the parasitic BJT,and it must be between BVCEO and BVCBO. The Hold voltage is to maintain Snap-back in a continuous ON state, but it cannot enter latch-up state; otherwise, it will enter secondary breakdown (thermal breakdown) and cause damage. Another concept is secondary breakdown current, which is the sudden increase in heat due to I^2*R after entering latch-up, leading to silicon melting. This needs to be limited, which can be done by controlling W/L or adding a current-limiting high resistance. The simplest and most commonly used method is to increase the distance of the Drain/increase the distance of the SAB (a common practice in ESD rules).

 

3. Gate-Couple ESD technology: As we just mentioned, the bottleneck of multi-finger ESD design is the uniformity of the turn-on. Suppose there are10 fingers, and during ESD discharge, these 10 fingers may not necessarily turn on simultaneously (usually due to breakdown). It is common to see only 2-3 fingers turn on first, which is due to the layout not allowing each finger's relative position and wire direction to be exactly the same. Once these 2-3 fingers turn on, the ESD current concentrates on these 2-3 fingers, while the others remain off, so their ESD protection capability is equivalent to only the protection capability of 2-3 fingers, not 10 fingers.

 

This is also the main reason why the component size has been made very large, but the ESD protection capability has not increased as expected. Increasing the area has not brought the anticipated ESD enhancement. What to do? It's actually quite simple: we need to lower Vt1 (Trigger voltage). We can increase the voltage at the gate to turn on the substrate first instead of breakdown, generating substrate current, which allows other fingers to also turn on and enter the conducting state, enabling each finger to bear the ESD current and truly exert the ESD effect of a large area.

 

However, this GCNMOS ESD design has a drawback: once the channel is turned on and current is generated, it can easily cause gate oxide breakdown. Therefore, it is not necessarily a very good ESD design solution. Moreover, the smaller the active area, the greater the influence of gate voltage, while the larger the active area, the harder it is to turn on snap-back, making it difficult to grasp.

 

4. There is also a complex ESD protection circuit: Silicon Controlled Rectifier (SCR), which is the PNPN structure of the parasitic CMOS we discussed earlier that triggers snap-back and latch-up,achieving circuit protection through ON/OFF. You can review it; just let the factors that suppress latch-up from the previous article occur, but it can only be applied to Layout, not to Process, otherwise latch-up will fail again.

 

Finally, the design of ESD is very profound. I am just throwing out some ideas for the FAB people to understand. Basically, there are several ESD solutions: resistive voltage division, diodes, MOS, parasitic BJT, SCR (PNPN structure), and so on. Moreover, ESD is not only related to Design but also to the FAB process, and the knowledge is very deep; I don't quite understand it myself.

 

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